Silicon Vapor Chamber with Hierarchical Micro-/Nano Wicks

• Published in: 2024 25th International Conference on Electronic Packaging Technology (ICEPT) pp. 1 - 5
• Main Authors: Zheng, Deyin, Yu, Xin, Chen, Lin, Wang, Wei
• Format: Conference Proceeding
• Language: English
• Published: IEEE 07.08.2024
• Subjects: Etching; Heating systems; Silicon; Temperature distribution; Thermal management; Thermal management of electronics; Thermal resistance; vapor chamber; wicks
• ISSN: 2836-9734
• DOI: 10.1109/ICEPT63120.2024.10668635

A two-step processing method is developed for the fabrication of micro- and nano hierarchical wick structures on silicon substrate. Deep reaction ion etching (DRIE) was used to fabricate the primary wick, while the secondary wick structure was formed by electrochemical (EC) etching on the surface of the primary wick. The processing results show that the fabricated hierarchical wick structures consist of dense arrays of microscale trench and a uniformly distributed nanoporous layer with pore diameters less than 50nm. The merit of these hierarchical structures was demonstrated by thermal tests on the silicon vapor chamber integrated with such wicks. A prototype of the vapor chamber with 30 mm × 25 mm × 1.5 mm in dimension was developed as a passive heat spreader for thermal management of electronics. Thermal performance results indicate that the integration of hierarchical wick structures can significantly reduce the thermal resistance by ~50% compared with samples integrated with only microwick structures. Such an optimization on the thermal resistance indicates that integration of such hierarchical wick could be a promising method for the optimization of silicon-based thermal management devices.