Hardware Implementation of Memristor-Based in-Memory Computing for Classification Tasks

• Published in: 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 126 - 130
• Main Authors: Eslami, Mohammad Reza, Takhtardeshir, Soheib, Sharif, Sarah, Banad, Yaser Mike
• Format: Conference Proceeding
• Language: English
• Published: IEEE 11.08.2024
• Subjects: Accuracy; Hardware; In-memory computing; Memristor; Memristors; Neuromorphic computing; Noise; On-chip learning; Proteus; Software algorithms; SPICE; Training
• ISSN: 1558-3899
• DOI: 10.1109/MWSCAS60917.2024.10658943

Recent advancements in neuromorphic computing hardware have primarily centered around the development of integrated circuits, along with the analysis and simulation of analog circuits using the SPICE program. However, a critical shortfall of SPICE is its incapacity to accommodate algorithms and circuits based on microcontrollers, posing challenges for implementing on-chip training necessary for in-memory computing. To bridge this gap, our paper explores the implementation of SPICE-compatible circuit designs in the Proteus circuit simulator. We integrate a memristor component and a neuron model featuring a sigmoid activation function into Proteus. Subsequently, we construct a neuromorphic accelerator comprising 30 memristors and 4 neurons to demonstrate on-chip training and inference processes using an Arduino microcontroller. Additionally, our study introduces an optimal learning algorithm tailored for training memristors and adjusting synaptic weights during the training phase. The designed peripheral circuits govern all memristors throughout both training and inferencing and formulate an algorithm to apply test data for evaluating network accuracy.