High-Level Synthesis Implementation of SAD for VVC Standard

The Versatile Video Coding (H.266/VVC) standard is the latest generation codec developed by the Joint Video Experts Team (JVET). The VVC standard improves the encoding performance compared to previous standards at the cost of an increase in computational complexity. Therefore, researchers focus on r...

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Bibliographic Details
Published in2024 IEEE 7th International Conference on Advanced Technologies, Signal and Image Processing (ATSIP) Vol. 1; pp. 83 - 86
Main Authors Abdallah, Bouthaina, Belghith, Fatma, Masmoudi, Nouri
Format Conference Proceeding
LanguageEnglish
Published IEEE 11.07.2024
Subjects
Codes
Computer architecture
High-level synthesis (HLS)
Power demand
Random access memory
Software algorithms
Sum of Absolute Difference (SAD)
Versatile Video Coding (H.266/VVC)
Video coding
Video sequences
Xilinx ZYNQ
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Summary:The Versatile Video Coding (H.266/VVC) standard is the latest generation codec developed by the Joint Video Experts Team (JVET). The VVC standard improves the encoding performance compared to previous standards at the cost of an increase in computational complexity. Therefore, researchers focus on reducing coding complexity through hardware acceleration. This paper introduces an efficient High-Level Synthesis (HLS) hardware design of the Sum of Absolute Difference (SAD) for the VVC encoder. In fact, different directives are initially employed to the SAD C code to generate an optimized hardware IP (Intellectual property) design, using Xilinx Vivado HLS platform. Then, using the Xilinx Vivado tool, this IP is implemented on the ZYNQ-7 ZC702 Evaluation Board. The synthesis report shows that the SW/HW design system requires power consumption of \mathbf{1. 7 3 6} \mathrm{W}, \mathbf{2 0 \%} of Look-up Tables (LUTs), \mathbf{4 \%} of RAM blocks and 6 \% of FlipFlops (FFs).
ISSN:2687-878X
DOI:10.1109/ATSIP62566.2024.10638861