A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications

This paper presents high-speed SRAM macros of 0.64Mbit ( 1024\times 640 ) and 1.28Mbit ( 2048\times 640 ) implemented using a high-current single port 6T bitcell. The macros achieve the best FoM defined as (density × frequency)/(read power + write power). Several performance-enhancing circuit techni...

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Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Huang, Ming-Chieh, Mar, Wei Wing, Kanade, Shankar, Bai, Boris, Gayatri, Aditya, Khairnar, Krishna, Lai, Amy, Hsu, Yu-Hao, Liao, Hung-Jen, Wang, Yih, Chang, Tsung-Yung Jonathan
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.06.2024
Subjects
3nm
Capacitance
Finance
FinFETs
Multi-bank
Random access memory
Repeaters
Single-port
SRAM
Very large scale integration
Voltage measurement
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Summary:This paper presents high-speed SRAM macros of 0.64Mbit ( 1024\times 640 ) and 1.28Mbit ( 2048\times 640 ) implemented using a high-current single port 6T bitcell. The macros achieve the best FoM defined as (density × frequency)/(read power + write power). Several performance-enhancing circuit techniques are proposed, including wordline, global clock, and global bitline boosting. Split drivers for decoder signals are proposed to achieve an overall 37% speed improvement while avoiding a repeater area tax. A read assist circuit is proposed to improve Vmax to 1.35V. Silicon results demonstrate the ability to achieve 3.3GHz at 1.0V/100°C in 3nm FinFET technology.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631546