An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology

This work presents a power impedance measurement (PIM) architecture for the 3D-IC platform with high-performance computing (HPC) applications. Proposed current-sink-free architecture improves stimulus current capacity without area overhead. Another adaptive-timing scheme saves 50% testing time. The...

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Bibliographic Details
Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Lu, Tsung-Che, Fu, Chin-Ming, Wang, Wei-Hsiang, Kuo, Fred, Chang, Chih-Hsien, Hsieh, Kenny, Tam, King-Ho, Huang, Tze-Chiang, Chen, Tom, Wong, Mei, Changchien, Wei-Pin, Lee, Frank
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.06.2024
Subjects
Computer architecture
FinFETs
High performance computing
Impedance measurement
IP networks
System-on-chip
Very large scale integration
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Summary:This work presents a power impedance measurement (PIM) architecture for the 3D-IC platform with high-performance computing (HPC) applications. Proposed current-sink-free architecture improves stimulus current capacity without area overhead. Another adaptive-timing scheme saves 50% testing time. The PIM IP has been fabricated in 5nm FinFET process with TSMC-SoIC® technology for characterization of an embedded ARM® core. Compared to state-of-the-art works, the 3.6-A stimulus current yields 116x improvement while the 0.006 mm 2 core area achieves 79% reduction.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631517