A Stochastic Analog SAT Solver in 65nm CMOS Achieving \mathbf\mathbf\mathbf Average Solution Time with 100% Solvability for Hard 3-SAT Problems
This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with continuous-time self-loopback pull-up switches, a discrete-time scrambling scheme, and a cost-efficient hybrid random code generator. The SAT prototype in 65nm CMOS achieves orders of magnitude improveme...
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Published in | 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2 |
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Main Authors | , , , , , , , , , , , |
Format | Conference Proceeding |
Language | English |
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IEEE
16.06.2024
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Abstract | This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with continuous-time self-loopback pull-up switches, a discrete-time scrambling scheme, and a cost-efficient hybrid random code generator. The SAT prototype in 65nm CMOS achieves orders of magnitude improvement in speed and energy efficiency compared to prior ASIC (digital and analog) SAT solvers. |
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AbstractList | This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with continuous-time self-loopback pull-up switches, a discrete-time scrambling scheme, and a cost-efficient hybrid random code generator. The SAT prototype in 65nm CMOS achieves orders of magnitude improvement in speed and energy efficiency compared to prior ASIC (digital and analog) SAT solvers. |
Author | Hossain, Sushmit Su, Shiyu Palaria, Mayank Chen, Buyun Liu, Zerui Chen, Mike Shuo-Wei Zhang, Qiaochu Qiu, Zhengyi Wu, Wei Cheng, Hsiang-Chun Meng, Deming Ye, Jiacheng |
Author_xml | – sequence: 1 givenname: Qiaochu surname: Zhang fullname: Zhang, Qiaochu organization: University of Southern California,Los Angeles,CA,USA – sequence: 2 givenname: Shiyu surname: Su fullname: Su, Shiyu organization: University of Southern California,Los Angeles,CA,USA – sequence: 3 givenname: Zerui surname: Liu fullname: Liu, Zerui organization: University of Southern California,Los Angeles,CA,USA – sequence: 4 givenname: Hsiang-Chun surname: Cheng fullname: Cheng, Hsiang-Chun organization: University of Southern California,Los Angeles,CA,USA – sequence: 5 givenname: Zhengyi surname: Qiu fullname: Qiu, Zhengyi organization: University of Southern California,Los Angeles,CA,USA – sequence: 6 givenname: Mayank surname: Palaria fullname: Palaria, Mayank organization: University of Southern California,Los Angeles,CA,USA – sequence: 7 givenname: Jiacheng surname: Ye fullname: Ye, Jiacheng organization: University of Southern California,Los Angeles,CA,USA – sequence: 8 givenname: Deming surname: Meng fullname: Meng, Deming organization: University of Southern California,Los Angeles,CA,USA – sequence: 9 givenname: Buyun surname: Chen fullname: Chen, Buyun organization: University of Southern California,Los Angeles,CA,USA – sequence: 10 givenname: Sushmit surname: Hossain fullname: Hossain, Sushmit organization: University of Southern California,Los Angeles,CA,USA – sequence: 11 givenname: Wei surname: Wu fullname: Wu, Wei organization: University of Southern California,Los Angeles,CA,USA – sequence: 12 givenname: Mike Shuo-Wei surname: Chen fullname: Chen, Mike Shuo-Wei organization: University of Southern California,Los Angeles,CA,USA |
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Snippet | This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with continuous-time self-loopback pull-up switches, a... |
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SubjectTerms | accelerator analog CMOS CMOS technology Codes COP Energy efficiency Generators Hybrid power systems Prototypes SAT stochastic Very large scale integration |
Title | A Stochastic Analog SAT Solver in 65nm CMOS Achieving \mathbf\mathbf\mathbf Average Solution Time with 100% Solvability for Hard 3-SAT Problems |
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