A Stochastic Analog SAT Solver in 65nm CMOS Achieving \mathbf\mathbf\mathbf Average Solution Time with 100% Solvability for Hard 3-SAT Problems

This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with continuous-time self-loopback pull-up switches, a discrete-time scrambling scheme, and a cost-efficient hybrid random code generator. The SAT prototype in 65nm CMOS achieves orders of magnitude improveme...

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Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Zhang, Qiaochu, Su, Shiyu, Liu, Zerui, Cheng, Hsiang-Chun, Qiu, Zhengyi, Palaria, Mayank, Ye, Jiacheng, Meng, Deming, Chen, Buyun, Hossain, Sushmit, Wu, Wei, Chen, Mike Shuo-Wei
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.06.2024
Subjects
accelerator
analog
CMOS
CMOS technology
Codes
COP
Energy efficiency
Generators
Hybrid power systems
Prototypes
SAT
stochastic
Very large scale integration
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Summary:This paper presents a stochastic analog SAT solver, featuring a fast open-loop architecture with continuous-time self-loopback pull-up switches, a discrete-time scrambling scheme, and a cost-efficient hybrid random code generator. The SAT prototype in 65nm CMOS achieves orders of magnitude improvement in speed and energy efficiency compared to prior ASIC (digital and analog) SAT solvers.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631503