A 640-Gb/s 4\times 4-MIMO D-Band CMOS Transceiver Chipset

This work presents aD-band (114-170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth. An 8-way low-Q power-combined power amplifier (P A), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded dist...

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Bibliographic Details
Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Liu, Chenxin, Li, Zheng, Yamazaki, Yudai, Herdian, Hans, Wang, Chun, Tian, Anyi, Sakamaki, Jun, Nie, Han, Fu, Xi, Kato, Sena, Wang, Wenqian, Huang, Hongye, Hara, Shinsuke, Kasamatsu, Akifumi, Sakai, Hiroyuki, Kunihiro, Kazuaki, Shirane, Atsushi, Okada, Kenichi
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.06.2024
Subjects
200Gb/s
640Gb/s
Bandwidth
CMOS
D-band
Linearity
Low-noise amplifiers
MIMO
Power amplifiers
Semiconductor device measurement
TRX
Very large scale integration
Wireless networks
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Summary:This work presents aD-band (114-170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth. An 8-way low-Q power-combined power amplifier (P A), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) are proposed to improve bandwidth and linearity. The proposed TRX chipset achieves 200-Gb/s data rate by 32QAM in the single-input single-output (SISO) over-the-air (OTA) measurement. A 120-Gb/s data rate by 16QAM is realized with a 15m distance. A 640-Gb /\mathrm{s} \ 4\times 4 multi-input multi-output (MIMO) is also demonstrated in this work.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631487