Field Plate and Package Optimization for GaN Devices and Systems

To improve GaN-based system performance, this work demonstrates the 650V GaN field plate (FP) design and the optimized integrated circuit (IC) package. The source FP length is suggested to be longer but less than three times the split high FP (HFP). The connection of the split FP and the 1^{\text{ST...

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Bibliographic Details
Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Hung, Sheng-Hsi, Wang, Tz-Wun, Cho, Chien-Wei, Chiu, Po-Jui, Chen, Chi-Yu, Chen, Ke-Horng, Zheng, Kuo-Lin, Li, Chih-Chen
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.06.2024
Subjects
Cooling
Optimization
Switches
System performance
Three-dimensional displays
Very large scale integration
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Summary:To improve GaN-based system performance, this work demonstrates the 650V GaN field plate (FP) design and the optimized integrated circuit (IC) package. The source FP length is suggested to be longer but less than three times the split high FP (HFP). The connection of the split FP and the 1^{\text{ST}} FP to source FP can reduce Coss. Longer 1^{\text{ST}} FP and shorter Gap design enhance the Miller ratio and suppress the ringing effect in case of switching. The asynchronous boost converter can be implemented with minimal parasitics and double-sided cooling in a proposed 3D IC package.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631457