Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process

A tapered stacked-gates device offers the advantages of saving area and reducing noise and mismatch, and it is universally applicable to many circuits. The proposed current-mirror design in bandgap reference (BGR) and current control oscillator (ICO) circuits use tapered stacked-gates for current mi...

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Bibliographic Details
Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Hsia, Chu-En, Chang, Chin-Ho, Chen, Yung-Shun, Lai, Po-Yu, Jen, Ching Lin, Peng, Yung-Chow, Li, Shenggao
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.06.2024
Subjects
Bandgap voltage reference
Current control oscillator
Current mirrors
Logic gates
Mismatch
MOS array layout and Current mirror
Noise
Performance evaluation
Photonic band gap
Process control
Stack gate
Very large scale integration
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Summary:A tapered stacked-gates device offers the advantages of saving area and reducing noise and mismatch, and it is universally applicable to many circuits. The proposed current-mirror design in bandgap reference (BGR) and current control oscillator (ICO) circuits use tapered stacked-gates for current mirror. Different numbers of transistors are used in the stacked stages, which reduces the number of source-side transistors and results in a 24% area reduction while maintaining the same mismatch and noise performance according to experimental result. In addition, using the same number of devices, this design can achieve better performance with almost 45% noise and 28% mismatch reduction in simulation. Overall, this non-formal stacked-gates transistor circuit design shows promising potential for analog circuit applications.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631454