4F2 Stackable Polysilicon Channel Access Device for Ultra-Dense NVDRAM

We report on the methodology and optimization used to enable a stackable 4F 2 polysilicon thin film transistor (TFT) for ultra-dense 32 Gb NVDRAM. Several key innovations are implemented to meet the strict thermal budget constraints required for a dual-layer technology. Confined heating from pulsed...

Full description

Saved in:
Bibliographic Details
Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 3
Main Authors Liao, A., Jerry, M., Karda, K., Hollander, M., Sharma, P., Ge, R., Zhao, T., Hajjam, G.K. El, Mariani, M., Calabrese, M., Raimondi, D., Rigano, A., Rossi, T., Florent, K., Tapias, N., Jacob, C., Calderoni, A., Chhajed, S., Zahurak, J., Ramaswamy, N.
Format Conference Proceeding
LanguageEnglish
Published IEEE 16.06.2024
Subjects
Annealing
Laser anneal
Logic gates
Materials reliability
NVDRAM
Performance evaluation
Polysilicon
Reliability engineering
Technological innovation
Thin film transistor
Very large scale integration
Online AccessGet full text

Cover

More Information
Summary:We report on the methodology and optimization used to enable a stackable 4F 2 polysilicon thin film transistor (TFT) for ultra-dense 32 Gb NVDRAM. Several key innovations are implemented to meet the strict thermal budget constraints required for a dual-layer technology. Confined heating from pulsed laser annealing is used to crystallize polysilicon and activate source/drain dopants. Material optimization is used to engineer both a gate oxide deposited at low temperatures capable of 10 years equivalent reliability and a Ru wordline (WL) robust to agglomeration and voiding failures. Device performance, robust to top layer processing, is matched across both layers by adjusting process conditions as informed by a TCAD model that accounts for heat transfer and crystallization dynamics.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46783.2024.10631429