A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology

• Published in: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
• Main Authors: Loscalzo, Erik, Cochet, Martin, Zuckerman, Joseph, Zalias, Samira, Lekas, Michael, Cahill, Stephen, Jia, Tianyu, Swaminathan, Karthik, dos Santos, Maico Cassel, Giri, Davide, Sadeghi, Hesam, Meyer, Joseph, Sturcken, Noah, Brooks, David, Wei, Gu-Yeon, Carloni, Luca, Bose, Pradip, Shepard, Kenneth
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16.06.2024
• Subjects: digital low-dropout regulator; Magnetic cores; Network-on-chip; package integrated voltage regulator; Power system management; Power system measurements; Regulators; Time-frequency analysis; unified voltage and frequency scaling; Very large scale integration
• ISSN: 2158-9682
• DOI: 10.1109/VLSITechnologyandCir46783.2024.10631353

We have developed a dynamic-voltage-and-frequency-scaling (DVFS) architecture that combines a package-integrated buck voltage regulator (PIVR) with fully standard-cell-based digital low-dropout regulators (LDO) to support fine-grained control at the scale of individual cores in a 22-core system-on-chip (SoC) with a settling time of 400ns. The PIVR has a power density of309mW/mm 2 and features full back-end integration of magnetic-core power inductors. During a workload study on the SoC consisting of four general-purpose RISC- V cores and 18 specialized accelerators, our hybrid voltage regulator (HVR) showed the highest power savings when compared with other power management techniques for workload durations above 1.3µs and peak power savings of 23% over the baseline without DVFS.