The design of Wishbone-IIC Master Bus Verification Platform Based on UVM

• Published in: 2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE) pp. 635 - 639
• Main Authors: Wang, Yang, Huang, Chuyun, Wu, Xiaoqiang, Gan, Neng
• Format: Conference Proceeding
• Language: English
• Published: IEEE 24.05.2024
• Subjects: Automation; Buildings; code coverage; Codes; component; Electronic circuits; Logic; Simulation; UVM; verification; Wishbone-IIC

UVM is the universal verification methodology that provides a hierarchical verification framework. The modularized design allows each component to be applied in different projects, greatly improving the efficiency and reusability of chip verification and shortening the development cycle of chips. In...