The design of Wishbone-IIC Master Bus Verification Platform Based on UVM

UVM is the universal verification methodology that provides a hierarchical verification framework. The modularized design allows each component to be applied in different projects, greatly improving the efficiency and reusability of chip verification and shortening the development cycle of chips. In...

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Bibliographic Details
Published in2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE) pp. 635 - 639
Main Authors Wang, Yang, Huang, Chuyun, Wu, Xiaoqiang, Gan, Neng
Format Conference Proceeding
LanguageEnglish
Published IEEE 24.05.2024
Subjects
Automation
Buildings
code coverage
Codes
component
Electronic circuits
Logic
Simulation
UVM
verification
Wishbone-IIC
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Summary:UVM is the universal verification methodology that provides a hierarchical verification framework. The modularized design allows each component to be applied in different projects, greatly improving the efficiency and reusability of chip verification and shortening the development cycle of chips. In this paper, we propose a method to verify the function of the Wishbone-IIC master bus based on UVM. The main research content can be summarized as follows: firstly, We have analyzed the internal structure of DUT (Design Under Test), and then established the verification platform based on the top-level design and UVM theory, and finally developed the verification plan and designing test cases to functionally test the logic of the DUT and analyze simulation results. The research results show that the final code coverage reaches 100 \%, which meets the requirement of the digital verification.
DOI:10.1109/ECIE61885.2024.10626777