Enhancing functional verification productivity through an automated workflow with Machine Learning based tools

• Published in: 2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV) pp. 166 - 170
• Main Authors: Nguyen, Chi Lan Phuong, Hoang, Quyet Van, Tran, An Hai Lam, Tran, Khoa Dac, Tran, Nghia Trong, Noguchi, Takafumi, David, James, Katogi, So, Endo, Yukie, Hirakimoto, Koji
• Format: Conference Proceeding
• Language: English
• Published: IEEE 06.06.2024
• Subjects: Debugging; Design automation; Functional Verification; Integrated circuit synthesis; Machine learning; Manuals; ML-based EDA tool; Productivity; Source coding
• DOI: 10.1109/ICDV61346.2024.10617255

As the demand for chips grows and high-performance processing requirements increase, chip designs have become larger and more complex. Consequently, the verification time for large-scale System on Chip (SoC) has dramatically increased. To keep up with this growth, there is a need to enhance the verification process and workflow, aiming to improve efficiency and productivity. In this paper, we propose a verification automation workflow driven by Machine Learning (ML)-based Electronic Design Automation (EDA) tools, which can enhance productivity in two key areas: regression testing and debugging of regression failures. By using this methodology, we can improve Turn-Around Time (TAT) by up to 40 \% while maintaining the same coverage for random test regression. Additionally, for debugging, the ML-based tool can help to automate the debugging process for regression failures, resulting in a workload reduction of up to 75 \% compared to the original workflow, specifically for four significant debugging issues: failure triage, bad revision detection, source code diff check and waveform difference identification.