Design of Low Power Area efficient SAR ADC at Submicron Level for Medical Application

• Published in: 2024 Second International Conference on Data Science and Information System (ICDSIS) pp. 1 - 5
• Main Authors: Naveen, I G, Vinith, U, Archana, R, Dhanush, A
• Format: Conference Proceeding
• Language: English
• Published: IEEE 17.05.2024
• Subjects: analog-to-digital converter; cmos; digital-to-analog converter; Latches; Measurement; Medical services; Power demand; Registers; successive approximation register; Switches; Voltage
• DOI: 10.1109/ICDSIS61070.2024.10594068

This paper provides the design and analysis of a 14-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) built using 45 nm CMOS technology. The SAR ADC uses a binary weighted capacitive digital-to-analog converter (CDAC) architecture to reduce power dissipation and overall chip space by employing an area-efficient and low-energy switching scheme. Further, it consists of a dynamic latch comparator which is used to reduce the overall power consumption of the architecture. The ring counter-based SAR logic block is implemented using D flip-flops to further reduce the chip area. The parallel output obtained from the SAR logic is then converted to serial bits using an encoder. The effectiveness of the proposed SAR ADC with weighted capacitors is assessed through transient analysis, with an emphasis on important performance metrics like resolution, power consumption and chip size. The results show that for 1 V voltage supply the power consumption is 407.36 \mu W with a chip area of 4077 \mu^{2}. The results obtained are able to enhance the accuracy and efficiency of power of SAR ADC over a wide range of low power applications.