A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology

A High-Speed High-Density 1R1W two port 32Kbit (128X256) SRAM with single port 6T bitcell macro is proposed. A Read-Then-Write (RTW) double pump CLK generation circuit with Tracking Bitline (TRKBL) bypassing is proposed to boost read and write performance. A Local Interlock Circuit (LIC) is introduc...

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Bibliographic Details
Published inIEEE solid-state circuits letters p. 1
Main Authors Zhang, Nick, Kim, Young Suk, Hsu, Peter, Kim, Samsoo, Tao, Derek, Liao, Hung-Jen, Wang, P.W., Yeap, Geoffrey, Li, Quincy, Chang, Tsung-Yung Jonathan
Format Journal Article
LanguageEnglish
Published IEEE 24.11.2023
Subjects
1R1W
5nm
Delays
double pump
FinFETs
Metals
Power demand
Random access memory
SRAM
Very large scale integration
Voltage
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Summary:A High-Speed High-Density 1R1W two port 32Kbit (128X256) SRAM with single port 6T bitcell macro is proposed. A Read-Then-Write (RTW) double pump CLK generation circuit with Tracking Bitline (TRKBL) bypassing is proposed to boost read and write performance. A Local Interlock Circuit (LIC) is introduced in Sense-Amp to reduce active power and push Fmax further. To mitigate metal RC degradation, Double Metal scheme is applied to improve signal integrity and enhance overall operating cycle time. The silicon results show that the slow corner wafer was able to achieve 4.24GHz at 1.0V/100C in 5nm FinFET technology.
ISSN:2573-9603
DOI:10.1109/LSSC.2023.3336773