A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12/spl sim/16 A) gate oxide

• Published in: 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) pp. 74 - 75
• Main Authors: Chung, S.S., Chen, S.-J., Yang, C.-K., Cheng, S.-M., Lin, S.-H., Sheng, Y.-C., Lin, H.-S., Hung, K.-T., Wu, D.-Y., Yew, T.-R., Chien, S.-C., Liou, F.-T., Wen, F.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Charge pumps; Current measurement; Electron traps; Electronics industry; Gate leakage; Industrial electronics; Leakage current; Monitoring; Tunneling; Voltage
• ISBN: 9780780373129; 078037312X
• DOI: 10.1109/VLSIT.2002.1015394

For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16 A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for various rapid thermal nitric oxide (RTNO) grown and remote plasma nitridation (RPN) treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.