Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology

Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a t...

Full description

Saved in:
Bibliographic Details
Published in2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303) pp. 62 - 63
Main Authors Schafbauer, T., Brighten, J., Yi-Cheng Chen, Clevenger, L., Commons, M., Cowley, A., Esmark, K., Grassmann, A., Hodel, U., Hsiang-Jen Huang, Shih-Fen Huang, Yimin Huang, Kaltalioglu, E., Knoblinger, G., Ming-Tsan Lee, Leslie, A., Pak Leung, Baozhen Li, Chuan Lin, Yi-Hsiung Lin, Nissl, W., Phung Nguyen, Olbrich, A., Riess, P., Rovedo, N., Sportouch, S., Thomas, A., Vietzke, D., Wendel, M., Robert Wong, Qiuyi Ye, Kun-Chi Lin, Schiml, T., Wann, C.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Artificial intelligence
Capacitance
Capacitors
CMOS technology
Dielectric substrates
Etching
Low voltage
Microelectronics
Radio frequency
Signal processing
Online AccessGet full text

Cover

More Information
Summary:Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.
ISBN:9780780373129
078037312X
DOI:10.1109/VLSIT.2002.1015388