A low-voltage low-noise digital buffer system

A novel low-voltage CMOS digital buffer is proposed. The primary characteristic of this digital buffer is the low voltage operation (V/sub DD/ between one and two transistor threshold voltages (V(/sub T//sup B/)), with a typical V/sub DD/ = 1.5V/sub T/). While operating at this reduced power supply,...

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Bibliographic Details
Published in2002 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 4; p. IV
Main Authors Secareanu, R.M., Peterson, B., Hartman, D.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Analog circuits
Circuit noise
Digital systems
Logic
Low voltage
Power dissipation
Power generation
Power supplies
Power system reliability
System-on-a-chip
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Summary:A novel low-voltage CMOS digital buffer is proposed. The primary characteristic of this digital buffer is the low voltage operation (V/sub DD/ between one and two transistor threshold voltages (V(/sub T//sup B/)), with a typical V/sub DD/ = 1.5V/sub T/). While operating at this reduced power supply, low noise and high overall performances are achieved.
ISBN:9780780374485
0780374487
DOI:10.1109/ISCAS.2002.1010419