Ultra-thin strained SOI substrate analysis by pseudo-MOS measurements

• Published in: Microelectronic engineering Vol. 80
• Main Authors: Gallon, C., Fenouillet-Beranger, C., Bresson, N., Cristoloveanu, Sorin, Allibert, Michel, Bord, S., Aulnette, C., Delille, Dominique, Latu-Romain, Eddy, Hartmann, Jean-Michel, Ernst, T., Andrieu, F., Campidelli, Y., Ghyselen, B., Cayrefourcq, I., Fournel, F., Kernevez, N., Skotnicki, T.
• Format: Journal Article
• Language: English
• Published: Elsevier 17.06.2005
• Subjects: Chemical Sciences; Material chemistry; ultra-thin strained SOI; pseudo-MOS measurements
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2005.04.074

Pseudo-MOS (Ψ -MOSFET) measurements are a simple and rapid technique for an accurate evaluation of SOI wafer intrinsic electrical properties, prior to any CMOS processing. For the first time, we report Ψ -MOSFET measurements performed on Strained SOI (SSOI) wafers with ultra-thin silicon films (9.5 nm to 17.5 nm). To take into account the wafer specificities and the use of such thin conduction layers, adapted Ψ -MOSFET models and parameter extraction methods were necessary. The experiments show an increase of the threshold and flat band voltages and a mobility reduction as the strained film becomes thinner. Further electrical analyses, coupled with several morphological studies, do not reveal any relaxation of the strain in the thinnest films. The mobility is clearly enhanced in SSOI as compared with standard SOI substrates.