A GEOMETRY STRUCTURE OF STATIC RANDOM ACCESS MEMORY (SRAM) FOR HIGH PERFORMANCE AND AREA ON CHIP

• Main Authors: Dr. Mali Madan Balkrishna, Mathurkar Piyush Kiranrao, Londhe Tanisha Sanjaykumar, Dr. Borhade Ratnaprabha Ravindra, Dr. Barekar Shital Sachin
• Format: Patent
• Language: English
• Published: 20.12.2023

On-chip cache memory based on Static Random Access Memory (SRAM) is widely used. Being the major part of the system-on-chip, it contributes the most important role in deciding the speed of operation, power dissipation, and area. High stability with more density and low power consumption is a vital part of modern system designs. In VDSM technology, the effect of temperature, process variation is challenging while designing the cache memory. For the reliable operation of the circuit, the design of the SRAM cell is projected. For maximum optimization of the layout area, 4-Cells alignment of cells in a row is proposed to achieve maximum density on a chip. This paper evaluates the effectiveness of the proposed alignment technique to increase the compactness of the SRAM array. With the effect of extracted parasitic elements, access time achieved is 340ps for 1KB of memory. The reduction in the area with the proposed alignment technique is 57.61% at the column level. The aspect ratio improved by 70.17 % with the proposed 4-Cells alignment technique.