METHOD AND DEVICE FOR SEALING IC CHIP

• Main Authors: ENCHI, KOHEI, KANAYAMA, SHINJI, OTANI, HIROYUKI, NISHINO, KENICHI, YOSHIDA, HIROYUKI
• Format: Patent
• Language: English; French; Japanese
• Published: 06.08.1998
• Edition: 6
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; SEMICONDUCTOR DEVICES; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION; TECHNICAL SUBJECTS COVERED BY FORMER USPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

A method and device for sealing IC chip, by which the occurence of imperfect sealing can be eleminated by surely feeding a sealing agent onto the upper surface of a mounting substrate. In the method, prior to feeding the sealing agent (17) a first gap (h1) is provided between a feeding nozzle (15) and the substrate (13) mounted with an IC chip (12), and the IC chip (12) is sealed while the sealing agent (17) is fed by providing a second gap (h2) larger than the first gap (h1) between the nozzle (15) and the substrate (13). After the sealing agent (17) is surely brought into contact with the upper surface of the substrate (13), the IC chip (12) is sealed. L'invention concerne un procédé et un dispositif pour sceller une puce de circuit intégré, qui permettent d'éliminer les risques de scellement imparfait en assurant de manière fiable le dépôt d'un agent de scellement à la surface supérieure d'un substrat de fixation. Selon le procédé, avant d'introduire l'agent de scellement (17), on ménage un premier espace (h1) entre une buse d'injection (15) et le substrat (13) où vient se fixer la puce de circuit intégré (12), laquelle sera scellée par l'agent de scellement (17) introduit au moment où un second espace (h2) plus important que le premier espace (h1) est ménagé entre la buse (15) et le substrat (13). Lorsque l'agent de scellement (17) est mis en contact de manière fiable avec la surface supérieure du substrat (13), la puce de circuit intégré (12) est scellée.