DISPLAY DEVICE

The present invention relates to a display device that can improve image quality by reducing parasitic capacitance between neighboring unit pixels, in which a first horizontal portion of a first gate node and a second horizontal portion of a second gate node each extend in a second direction interse...

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Bibliographic Details
Main Authors KANG, Chul Kyu, JEONG, Seon I, HYUN, Chae Han, KIM, Dong Hyun, KIM, Su Jin, MOK, Seon Kyoon, HWANG, Sung Chan
Format Patent
LanguageEnglish
French
Korean
Published 04.07.2024
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Summary:The present invention relates to a display device that can improve image quality by reducing parasitic capacitance between neighboring unit pixels, in which a first horizontal portion of a first gate node and a second horizontal portion of a second gate node each extend in a second direction intersecting a first direction, wherein at least a portion of the first horizontal portion and at least a portion of the second horizontal portion are disposed between opposing surfaces of a first pixel electrode and a second pixel electrode so as not to overlap with the first pixel electrode and the second pixel electrode. La présente invention concerne un dispositif d'affichage qui peut améliorer la qualité d'image en réduisant la capacité parasite entre pixels unitaires voisins, dans lequel une première partie horizontale d'un premier nœud de grille et une seconde partie horizontale d'un second nœud de grille s'étendent chacune dans une seconde direction croisant une première direction, au moins une partie de la première partie horizontale et au moins une partie de la seconde partie horizontale étant disposées entre des surfaces opposées d'une première électrode de pixel et d'une seconde électrode de pixel de façon à ne pas chevaucher la première électrode de pixel et la seconde électrode de pixel. 본 발명은 이웃하는 단위 화소들 간의 기생 커패시턴스를 줄여 화질을 향상시킬 수 있는 표시 장치에 관한 것으로, 제1 게이트 노드의 제1 수평부 및 제2 게이트 노드의 제2 수평부는 각각 제1 방향과 교차하는 제2 방향으로 연장되고, 제1 수평부의 적어도 일부 및 제2 수평부의 적어도 일부는, 제1 화소 전극 및 제2 화소 전극과 중첩하지 않도록, 제1 화소 전극과 상기 제2 화소 전극의 마주보는 면들 사이에 배치된다.
Bibliography:Application Number: WO2023KR21127