CHIP AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE

• Main Authors: FAN, Rongwei, HUANG, Weichuan, SHI, Zhijie, MA, Ye
• Format: Patent
• Language: Chinese; English; French
• Published: 04.04.2024
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

Embodiments of the present application relate to the technical field of semiconductors, and provide a chip and a manufacturing method therefor, and an electronic device, for use in solving the problem of how to improve the interconnection coupling effect between conductive patterns in a chip. The chip provided by the present application may be a bare die or a packaged chip. The chip comprises a dielectric layer, a conductive column running through the dielectric layer, a first conductive pattern, a second conductive pattern, and a filling layer; the first conductive pattern and the second conductive pattern are located on two sides of the dielectric layer, respectively; the two ends of the conductive column are respectively in contact with the first conductive pattern and coupled with the second conductive pattern; the filling layer is used for covering at least part of the side surface of the conductive column and filling a gap between the conductive column and the dielectric layer. The present application i