LOW RESISTANCE MOLYBDENUM DEPOSITION FOR LOGIC SOURCE/DRAIN CONTACTS

• Main Authors: MANDIA, David Joseph, NA, Jeong-Seok, GRIFFITHS, Matthew Bertram Edward, LAI, Chiukin Steven, HSIEH, Yao-Tsung
• Format: Patent
• Language: English; French
• Published: 31.08.2023
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION

Provided is an efficient method for filling a semiconductor substrate conformal layer lined feature utilizing a metal precursor to selectively deposit metal at the bottom of the feature and to etch the conformal layer lining from feature sidewalls. L'invention concerne un procédé efficace pour remplir un élément chemisé d'une couche conforme de substrat semi-conducteur à l'aide d'un précurseur métallique afin de déposer sélectivement du métal sur la partie inférieure de l'élément et afin de graver le revêtement intérieur de couche conforme à partir des parois latérales de l'élément.