3-DIMENSIONAL NEUROMORPHIC SYSTEM AND OPERATION METHOD THEREOF

• Main Authors: LEE, Yoon Myung, CHOI, Chang Hwan, JEON, Yu Rim, SEO, Dong Uk
• Format: Patent
• Language: English; French; Korean
• Published: 29.12.2022
• Subjects: CALCULATING; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS; COMPUTING; COUNTING; INFORMATION STORAGE; PHYSICS; STATIC STORES

The present invention relates to a technology for independently connecting and forming, through interconnection layers, a plurality of neuromorphic devices that are 3-dimensionally stacked and formed on a complementary metal-oxide semiconductor (CMOS) wafer, and selectively driving and testing the plurality of neuromorphic devices through a pulse generated and transmitted by the CMOS wafer, and according to an embodiment, a 3-dimensional neuromorphic system implemented on a CMOS wafer may comprise: a device array unit comprising a plurality of neuromorphic devices independently connected to a plurality of interconnection layers formed on the CMOS wafer, respectively; a synaptic pulse generation unit for generating at least one synaptic pulse such that the plurality of neuromorphic devices generate synaptic characteristics; and a control unit that generates a control signal for controlling the generation of the at least one synaptic pulse and controls the generated at least one synaptic pulse to be sequentially applied to the plurality of neuromorphic devices. La présente invention concerne une technologie consistant à connecter et à former indépendamment, par l'intermédiaire de couches d'interconnexion, une pluralité de dispositifs neuromorphiques qui sont empilés et formés en trois dimensions sur une tranche de semi-conducteur à oxyde métallique complémentaire (CMOS), et à commander et à tester sélectivement la pluralité de dispositifs neuromorphiques par l'intermédiaire d'une impulsion générée et transmise par la tranche de CMOS et, selon un mode de réalisation, un système neuromorphique en trois dimensions implémenté sur une tranche de CMOS peut comprendre : une unité de réseau de dispositifs comprenant une pluralité de dispositifs neuromorphiques connectés indépendamment respectivement à une pluralité de couches d'interconnexion formées sur la tranche de CMOS ; une unité de génération d'impulsions synaptiques servant à générer au moins une impulsion synaptique de sorte que la pluralité de dispositifs neuromorphiques génèrent des caractéristiques synaptiques ; et une unité de commande qui génère un signal de commande servant à commander la génération de ladite impulsion synaptique et qui commande ladite impulsion synaptique générée à appliquer successivement à la pluralité de dispositifs neuromorphiques. 본 발명은 CMOS(Complementary Metal-Oxide Semiconductor) 웨이퍼(wafer)에서 3차원 적층 형성된 복수의 뉴로모픽 소자를 상호 연결층을 통해 독립적으로 연결 형성하고, CMOS 웨이퍼에서 발생 및 전달하는 펄스(pulse)로 복수의 뉴로모픽 소자를 선택적으로 구동 및 테스트 하는 기술에 관한 것으로, 일실시예에 따르면 3차원 뉴로모픽 시스템은 CMOS(Complementary Metal-Oxide Semiconductor) 웨이퍼(wafer) 상에 구현되는 3차원 뉴로모픽 시스템으로서, 상기 CMOS(Complementary Metal-Oxide Semiconductor) 웨이퍼(wafer) 상에 형성된 복수의 상호 연결층 각각과 독립적으로 연결된 복수의 뉴로모픽 소자를 포함하는 소자 어레이부, 상기 복수의 뉴로모픽 소자에서 시냅틱(Synaptic) 특성을 발생시키도록 적어도 하나의 시냅틱 펄스를 생성하는 시냅틱 펄스 생성부 및 상기 적어도 하나의 시냅틱 펄스의 생성을 제어하기 위한 제어 신호를 생성하고, 상기 복수의 뉴로모픽 소자에 상기 생성된 적어도 하나의 시냅틱 펄스가 순차적으로 인가되도록 제어하는 제어부를 포함할 수 있다.