LOW-LATENCY OPTICAL CONNECTION FOR CXL FOR A SERVER CPU

A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream dire...

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Bibliographic Details
Main Authors NALAMALPU, Ankireddy, HOSSAIN, MD Altaf, KUMASHIKAR, Mahesh, SUBBAREDDY, Dheeraj, THAKUR, Anshuman
Format Patent
LanguageEnglish
French
Published 14.04.2022
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION
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Summary:A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path. Un processeur ayant une architecture de système sur puce (SOC) comprend une ou plusieurs unités centrales de traitement (CPU) comprenant de multiples cœurs. Une voie de communication Compute Express Link (CXL) optique incorporant un chemin de pile de protocoles CXL optique logique permet d'émettre et de recevoir un flux binaire optique directement après la couche liaison, contournant de multiples niveaux de la pile de protocoles CXL. Un contrôleur d'interface CXL est connecté à la ou aux CPU pour permettre une communication entre les CPU et un ou plusieurs dispositifs CXL sur la voie de communication CXL optique.
Bibliography:Application Number: WO2021US47987