INSTRUCTION CACHE PREFETCH THROTTLE

Techniques for controlling prefetching of instructions into an instruction cache are provided. Embodiments describe methods, instruction fetching systems, and processors for tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the...

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Bibliographic Details
Main Authors THYAGARAJAN, Aparna, WONG, Angelo, JONES, William E, VENKATACHAR, Ashok Tirupathy, EVERS, Marius
Format Patent
LanguageEnglish
French
Published 17.06.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Techniques for controlling prefetching of instructions into an instruction cache are provided. Embodiments describe methods, instruction fetching systems, and processors for tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the tracking, and adjusting prefetch activity based on the throttle toggle. La présente invention concerne des techniques de commande de prélecture d'instructions dans une mémoire cache d'instructions. Des modes de réalisation décrivent des procédés, des systèmes de lecture d'instructions, et des processeurs permettant de suivre des absences de tampon cible de ramification (BTB) et/ou des absences de mémoire cache d'instruction, modifier une bascule de limitation sur la base du suivi, et ajuster une activité de prélecture sur la base de la bascule de limitation.
Bibliography:Application Number: WO2020US61373