DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND METHOD FOR MANUFACTURING SAME
A display device according to an embodiment of the present invention is characterized by comprising: a base part; a first electrode formed on the base part; a dielectric layer stacked on one surface of the first electrode; a second electrode disposed on the dielectric layer at a predetermined interv...
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Main Authors | , |
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Format | Patent |
Language | English French Korean |
Published |
17.06.2021
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Subjects | |
Online Access | Get full text |
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Summary: | A display device according to an embodiment of the present invention is characterized by comprising: a base part; a first electrode formed on the base part; a dielectric layer stacked on one surface of the first electrode; a second electrode disposed on the dielectric layer at a predetermined interval; a barrier rib portion stacked on the dielectric layer to cover the second electrode while forming a plurality of cells; and semiconductor light emitting elements mounted on the cells, wherein the first electrode may be spaced apart from the second electrode with the dielectric layer interposed therebetween.
La présente invention concerne un dispositif d'affichage qui selon un mode de réalisation est caractérisé en ce qu'il comprend : une partie de base ; une première électrode formée sur la partie de base ; une couche diélectrique empilée sur une surface de la première électrode ; une seconde électrode disposée sur la couche diélectrique à un intervalle prédéterminé ; une partie nervure de barrière empilée sur la couche diélectrique pour recouvrir la seconde électrode tout en formant une pluralité de cellules ; et des éléments électroluminescents à semi-conducteurs montés sur les cellules, la première électrode pouvant être espacée de la seconde électrode, la couche diélectrique étant interposée entre celles-ci.
본 발명의 실시예에 따른 디스플레이 장치는 베이스부; 상기 베이스부 상에 형성되는 제1 전극; 상기 제1 전극의 일면에 적층되는 유전체층; 상기 유전체층 상에 소정 간격으로 배치되는 제2 전극; 복수의 셀을 형성하면서, 상기 제2 전극을 덮도록 상기 유전체층 상에 적층되는 격벽부; 및 상기 셀에 안착되는 반도체 발광소자들을 포함하고, 상기 제1 전극은, 상기 유전체층을 사이에 두고 상기 제2 전극과 이격 배치되는 것을 특징으로 한다. |
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Bibliography: | Application Number: WO2019KR17957 |