BIAS SCHEME FOR WORD PROGRAMMING IN NON-VOLATILE MEMORY AND INHIBIT DISTURB REDUCTION

A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory t...

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Main Authors RAMKUMAR, Krishnaswamy, KESHAVARZI, Ali, PRABHAKAR, Venkatraman, MENEZES, Gary
Format Patent
LanguageEnglish
French
Published 23.05.2019
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed. L'invention concerne un dispositif de mémoire qui comprend un réseau de mémoire non volatile (NVM), divisé en une partie de mémoire flash et une partie de mémoire morte programmable effaçable électriquement (EEPROM). Le réseau NVM comprend des cellules mémoires à piégeage de charge agencées en rangées et en colonnes, chaque cellule de mémoire comportant un transistor de mémoire comprenant un implant de drain légèrement dopé (LDD) incliné, et un transistor de sélection comprenant une région de source partagée avec un implant en halo. La partie de mémoire flash et la partie EEPROM sont disposées à l'intérieur d'une seule puce semi-conductrice. D'autres modes de réalisation sont également décrits.
Bibliography:Application Number: WO2018US57799