WAFER AND MANUFACTURING METHOD THEREFOR
An embodiment of a wafer manufacturing method may comprise: an ingot growing step of producing an ingot having a single crystal silicon structure; a sub-substrate manufacturing step of manufacturing a sub-substrate by processing the ingot; a poly silicon deposition step of depositing a thin film lay...
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Format | Patent |
Language | English French Korean |
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15.02.2018
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Abstract | An embodiment of a wafer manufacturing method may comprise: an ingot growing step of producing an ingot having a single crystal silicon structure; a sub-substrate manufacturing step of manufacturing a sub-substrate by processing the ingot; a poly silicon deposition step of depositing a thin film layer having a poly silicon structure on the sub-substrate; a wafer polishing step of polishing an upper surface of the thin film layer; a wafer cleaning step of cleaning the wafer; and a post-treatment step which is performed after completion of the wafer cleaning step.
Un mode de réalisation d'un procédé de fabrication de tranche peut comprendre : une étape de croissance de lingot consistant à produire un lingot ayant une structure de silicium monocristallin; une étape de fabrication de sous-substrat consistant à fabriquer un sous-substrat par traitement du lingot; une étape de dépôt de polysilicium consistant à déposer une couche de film mince ayant une structure de polysilicium sur le sous-substrat; une étape de polissage de tranche consistant à polir une surface supérieure de la couche de film mince; une étape de nettoyage de tranche consistant à nettoyer la tranche; et une étape de post-traitement qui est effectuée après l'achèvement de l'étape de nettoyage de tranche.
웨이퍼 제조방법의 일 실시예는, 단결정실리콘 구조의 잉곳을 제작하는 잉곳 성장단계; 상기 잉곳을 가공하여 서브기판을 제작하는 서브기판 제작단계; 상기 서브기판 상측에 폴리실리콘(poly silicon) 구조의 박막층의 증착공정을 진행하는 폴리실리콘 증착단계; 상기 박막층 상면을 연마하는 웨이퍼 연마단계; 상기 웨이퍼를 세척하는 웨이퍼 클리닝단계; 및 상기 웨이퍼 클리닝단계 완료 후 진행되는 후처리 단계를 포함하는 것일 수 있다. |
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AbstractList | An embodiment of a wafer manufacturing method may comprise: an ingot growing step of producing an ingot having a single crystal silicon structure; a sub-substrate manufacturing step of manufacturing a sub-substrate by processing the ingot; a poly silicon deposition step of depositing a thin film layer having a poly silicon structure on the sub-substrate; a wafer polishing step of polishing an upper surface of the thin film layer; a wafer cleaning step of cleaning the wafer; and a post-treatment step which is performed after completion of the wafer cleaning step.
Un mode de réalisation d'un procédé de fabrication de tranche peut comprendre : une étape de croissance de lingot consistant à produire un lingot ayant une structure de silicium monocristallin; une étape de fabrication de sous-substrat consistant à fabriquer un sous-substrat par traitement du lingot; une étape de dépôt de polysilicium consistant à déposer une couche de film mince ayant une structure de polysilicium sur le sous-substrat; une étape de polissage de tranche consistant à polir une surface supérieure de la couche de film mince; une étape de nettoyage de tranche consistant à nettoyer la tranche; et une étape de post-traitement qui est effectuée après l'achèvement de l'étape de nettoyage de tranche.
웨이퍼 제조방법의 일 실시예는, 단결정실리콘 구조의 잉곳을 제작하는 잉곳 성장단계; 상기 잉곳을 가공하여 서브기판을 제작하는 서브기판 제작단계; 상기 서브기판 상측에 폴리실리콘(poly silicon) 구조의 박막층의 증착공정을 진행하는 폴리실리콘 증착단계; 상기 박막층 상면을 연마하는 웨이퍼 연마단계; 상기 웨이퍼를 세척하는 웨이퍼 클리닝단계; 및 상기 웨이퍼 클리닝단계 완료 후 진행되는 후처리 단계를 포함하는 것일 수 있다. |
Author | KIM, Jae Sun KIM, In Kyum RYU, Kyoung Min JANG, Kyu Il |
Author_xml | – fullname: RYU, Kyoung Min – fullname: KIM, In Kyum – fullname: JANG, Kyu Il – fullname: KIM, Jae Sun |
BookMark | eNrjYmDJy89L5WRQD3d0cw1ScPRzUfB19At1c3QOCQ3y9HNX8HUN8fB3UQjxcA1ydfMP4mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8eH-RgaGFgbGBmZmZo6GxsSpAgBeniZ4 |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | 웨이퍼 및 그 제조방법 TRANCHE ET SON PROCÉDÉ DE FABRICATION |
ExternalDocumentID | WO2018030666A1 |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_WO2018030666A13 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 16:16:29 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English French Korean |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_WO2018030666A13 |
Notes | Application Number: WO2017KR07807 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180215&DB=EPODOC&CC=WO&NR=2018030666A1 |
ParticipantIDs | epo_espacenet_WO2018030666A1 |
PublicationCentury | 2000 |
PublicationDate | 20180215 |
PublicationDateYYYYMMDD | 2018-02-15 |
PublicationDate_xml | – month: 02 year: 2018 text: 20180215 day: 15 |
PublicationDecade | 2010 |
PublicationYear | 2018 |
RelatedCompanies | SK SILTRON CO., LTD |
RelatedCompanies_xml | – name: SK SILTRON CO., LTD |
Score | 3.0903387 |
Snippet | An embodiment of a wafer manufacturing method may comprise: an ingot growing step of producing an ingot having a single crystal silicon structure; a... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
Title | WAFER AND MANUFACTURING METHOD THEREFOR |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180215&DB=EPODOC&locale=&CC=WO&NR=2018030666A1 |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_GFPVNp-LHlIJSn4rrkrb2YUjXpBSh7Sit29voJwzFDVfx3_cSO93T3pIcXD7gcvdL7gPgnmZ6MaiyWjMtWmrUHJRaXumimrteoMIQRoh0kA1NP6UvM2PWgfdNLIzME_otkyOiRBUo7428r1f_j1hM-lauH_MFDi2fvWTE1BYdi3RmuqGy8YhPIha5qusiblPD-JdGhLHuIFbaQ0PaEvLAX8ciLmW1rVS8Y9ifIL-P5gQ6b8seHLqb2ms9OAjaL29sttK3PoWHqePxWHFCpgROmHqOm6TCmUEJeOJHTEl8HnNEdWdw5_HE9TWccf63wfk02l4eOYcuQv_qAhSSE1JSq87QbqC2RewnI8tyYtXDmtg0G15Cfxenq93kazgSXeGDrBt96DafX9UNqtgmv5Un8wMuhnmg |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LS8NAEB5KFetNq2K1akCJp2DT3STmUCRNNkRtkhIS21vIE0SxxUb8-87GVHvqbdmB2QfMzny7384A3NBEzgZFUkqqRnOJqoNcSguZV3OXM3QYPAipCbKe6kT0aa7MW_C-_gtT5wn9rpMjokVlaO9VfV4v_y-xrJpbubpLX7Fr8WCHI0ts0DFPZyYrojUesalv-aZomojbRC_4lREerBuIlXYwyNa4PbCXMf-Xstx0KvYB7E5R30d1CK23RRc65rr2Whf23ObJG5uN9a2O4HZm2CwQDM8SXMOLbMMMI05mEFwWOr4lhA4LGKK6Y7i2WWg6Eo4Y_y0wnvmb0yMn0EboX5yCQFJCcqqVCcYNVNeIfq8kSUq0clgSnSbDHvS3aTrbLr6CjhO6k3jy6D2fwz4XcT6yrPShXX1-FRfobqv0st6lHw20fJM |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=WAFER+AND+MANUFACTURING+METHOD+THEREFOR&rft.inventor=RYU%2C+Kyoung+Min&rft.inventor=KIM%2C+In+Kyum&rft.inventor=JANG%2C+Kyu+Il&rft.inventor=KIM%2C+Jae+Sun&rft.date=2018-02-15&rft.externalDBID=A1&rft.externalDocID=WO2018030666A1 |