MECHANISM TO ACCELERATE GRAPHICS WORKLOADS IN A MULTI-CORE COMPUTING ARCHITECTURE

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the...

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Bibliographic Details
Main Authors WOOP, Sven, WALD, Ingo, BENTHIN, Carsten
Format Patent
LanguageEnglish
French
Published 08.02.2018
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core. L'invention concerne un appareil de traitement. L'appareil comprend une pluralité de cœurs de traitement, comprenant un premier cœur de traitement et un second cœur de traitement, un premier réseau prédiffusé programmable par l'utilisateur (FPGA) couplé au premier cœur de traitement pour accélérer l'exécution des charges de travail graphiques traitées au niveau du premier cœur de traitement et un second FPGA couplé au second cœur de traitement pour accélérer l'exécution des charges de travail traitées au niveau du second cœur de traitement.
Bibliography:Application Number: WO2017US41746