REFRESH TIMER SYNCHRONIZATION BETWEEN MEMORY CONTROLLER AND MEMORY

A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles. L'invention concerne un contrôleur de m...

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Bibliographic Details
Main Authors JOSE, Edwin, DROP, Michael
Format Patent
LanguageEnglish
French
Published 06.04.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles. L'invention concerne un contrôleur de mémoire conçu pour signaler à une mémoire vive dynamique (DRAM) une indication du moment auquel s'est produit le cycle de rafraîchissement le plus récent déclenché par un contrôleur de mémoire avant une transition vers un mode de fonctionnement à auto-rafraîchissement dans lequel la DRAM auto-déclenche ses cycles de rafraîchissement.
Bibliography:Application Number: WO2016US48771