HIGH-EFFICIENCY ACTIVE CIRCUIT

Harmonic processing circuits (3a, 3b), which improve the efficiency of a transistor (1), are constituted by connecting, in parallel, distributed lines (4a, 4b) with electrical lengths of less than 90° at the second harmonic frequency (2fo) of the operating frequency of the transistor (1), and a capa...

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Bibliographic Details
Main Authors YAMAUCHI, KAZUHISA, NAKAHARA, KAZUHIKO, OGURA, SATOSHI, UCHIDA, HIROMITSU, NAKAYAMA, MASATOSHI
Format Patent
LanguageEnglish
French
Japanese
Published 29.11.2012
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Summary:Harmonic processing circuits (3a, 3b), which improve the efficiency of a transistor (1), are constituted by connecting, in parallel, distributed lines (4a, 4b) with electrical lengths of less than 90° at the second harmonic frequency (2fo) of the operating frequency of the transistor (1), and a capacitive coupling line that is interdigitally intersected by open-circuited stubs (5a, 5b) with electrical lengths of less than 90° at the second harmonic frequency (2fo). Selon l'invention, des circuits de traitement d'harmoniques (3a, 3b), qui améliorent l'efficacité d'un transistor (1), sont constitués par connexion, en parallèle, de lignes distribuées (4a, 4b) ayant des longueurs électriques de moins de 90° à la fréquence de seconde harmonique (2fo) de la fréquence de fonctionnement du transistor (1), et une ligne de couplage capacitif qui est coupée de façon interdigitée par des branches en circuit ouvert (5a, 5b) ayant des longueurs électriques de moins de 90° à la fréquence de seconde harmonique (2fo).
Bibliography:Application Number: WO2012JP03341