ARRAY ARCHITECTURE FOR REDUCED VOLTAGE, LOW POWER SINGLE POLY EEPROM

• Main Authors: STIEGLER, HARVEY, J, MITCHELL, ALLAN, T
• Format: Patent
• Language: English; French
• Published: 26.01.2012
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of eac...