VOLTAGE STABILIZATION FOR CLOCK SIGNAL FREQUENCY LOCKING

A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage suppl...

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Bibliographic Details
Main Authors ALLAREY, JOSE, JAHAGIRDAR, SANJEEV, HARRERA, IVAN
Format Patent
LanguageEnglish
French
Published 01.04.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A processor, system, and method are disclosed. In an embodiment, the processor includes a first site and a second site. There is a link to transmit a voltage stabilization signal from the second site to the first site. In the first site voltage correction logic can dynamically modify a voltage supplied to the first site and second site. In the second site there is logic to assert the voltage stabilization signal. After asserting the voltage stabilization signal, the second site is granted at least a window of time in which the supplied voltage to the second site does not change. La présente invention concerne un processeur, un système et un procédé. Dans un mode de réalisation, le processeur comprend un premier site et un second site. Une liaison transmet un signal de stabilisation de tension depuis le second site vers le premier site. Dans le premier site, une logique de correction de tension peut modifier dynamiquement une tension fournie au premier site et au second site. Dans le second site, une logique affirme le signal de stabilisation de tension. Après affirmation du signal de stabilisation de tension, le second site se voit accorder au moins une fenêtre temporelle dans laquelle la tension fournie au second site ne change pas.
Bibliography:Application Number: WO2009US57780