ARITHMETIC PROCESSING UNIT AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT

A shared L2 cache section (102A) in a CPU (100a) serving as a multicore processor has a shared PFPORT (102j) shared by a plurality of CPU core sections(101) in addition to PFPORTs (102b) provided for every CPU core section(101). The shared PFPORT (102j) secures an entry upon the event of uncompletin...

Full description

Saved in:
Bibliographic Details
Main Author HIKICHI, TORU
Format Patent
LanguageEnglish
French
Japanese
Published 27.08.2009
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online AccessGet full text

Cover

More Information
Summary:A shared L2 cache section (102A) in a CPU (100a) serving as a multicore processor has a shared PFPORT (102j) shared by a plurality of CPU core sections(101) in addition to PFPORTs (102b) provided for every CPU core section(101). The shared PFPORT (102j) secures an entry upon the event of uncompleting of a prefetch request placed from the PFPORTs (102b) to an L2 pipeline processing section (102f). An uncompleted prefetch request is placed again from the shared PFPORT (102j) to the L2 pipeline processing section (102f). L'invention concerne une section de mémoire cache L2 partagée (102A) dans un processeur (100a) servant de processeur multicoer. La section comporte un PFPORT partagé (102j), partagé par une pluralité de sections de coer de processeur (101) en plus de PFPORT (102b) fournis pour chaque section de coer de processeur (101). Le PFPORT partagé (102j) sécurise une entrée lors de l'événement d'inachèvement d'une demande de prélecture placée par les PFPORT (102b) sur une section de traitement de pipeline L2 (102f). Une demande de prélecture inachevée est à nouveau placée par le PFPORT partagé (102j) sur la section de traitement de pipeline L2 (102f).
Bibliography:Application Number: WO2008JP52652