CHARGE-TRAPPING MEMORY ARRAYS

The present invention relates to a memory array (100) comprising a substrate (222) and a plurality of bitlines (224) having contacts (240) and a plurality of wordlines (201, 202) intersecting the bitlines (224). A protective spacer (234) is used to separate the bitline contacts (240) from the wordli...

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Bibliographic Details
Main Authors CHEUNG, FRED, TK, KAMAL, TAZRIEN, RAMSBEY, MARK, T, SHIRAIWA, HIDEHIKO
Format Patent
LanguageEnglish
French
Published 28.10.2004
Edition7
Subjects
ELECTRICITY
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Summary:The present invention relates to a memory array (100) comprising a substrate (222) and a plurality of bitlines (224) having contacts (240) and a plurality of wordlines (201, 202) intersecting the bitlines (224). A protective spacer (234) is used to separate the bitline contacts (240) from the wordlines (201) adjacent to the bitline contacts (240) to prevent damage caused during the formation of the bitline contacts (240). The present invention also relates to a method of forming the memory array. L'invention concerne un réseau mémoire (100) comprenant un substrat (222) et une pluralité de lignes binaires (224) possédant des contacts (240) et une pluralité de lignes de mots (201, 202) croisant les lignes binaires (224). Un espaceur protecteur (234) est utilisé pour séparer les contacts (240) des lignes binaires des lignes de mots (201) adjacentes aux contacts (240) des lignes binaires, de manière à empêcher l'apparition d'un dommage engendré pendant la formation des contacts (240) des lignes binaires. L'invention concerne également un procédé de formation du réseau mémoire.
Bibliography:Application Number: WO2004US00502