REGISTER FILE GATING TO REDUCE MICROPROCESSOR POWER DISSIPATION

• Main Authors: GARG, MANISH, TERECHKO, ANDREI
• Format: Patent
• Language: English; French
• Published: 17.06.2004
• Edition: 7
• Subjects: CALCULATING; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION ANDCOMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION ANDCOMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THIR OWNENERGY USE; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; PHYSICS; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE

A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto. Agencement de circuit et procédé de régulation de la dissipation de puissance qui repose sur l'utilisation d'une pile (60) de registres à capacités de régulation de la dissipation de puissance via une configuration de registres en bancs couplés à une logique de validation (62, 82) configurée pour désactiver sélectivement les bancs non utilisés (70) de registres par blocage sélectif des entrées d'horloge (74), d'adresses (76) et de données (78) fournies à ces registres.