TRI-LAYER MASKING ARCHITECTURE FOR PATTERNING DUAL DAMASCENE INTERCONNECTS

This invention relates to a method of dual damascene integration for copper based wiring in a low-k dielectric stack (120, 130, 140) using three top hard mask layers (150, 160, 170) having alternating etch selectivity characteristics, and being, for example, inorganic/organic/inorganic. L'inven...

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Bibliographic Details
Main Authors TOWNSEND, PAUL, H., III, MILLS, LYNNE, K, STRITTMATTER, RICHARD, J, WAETERLOOS, JOOST, J., M
Format Patent
LanguageEnglish
French
Published 04.11.2004
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:This invention relates to a method of dual damascene integration for copper based wiring in a low-k dielectric stack (120, 130, 140) using three top hard mask layers (150, 160, 170) having alternating etch selectivity characteristics, and being, for example, inorganic/organic/inorganic. L'invention concerne un procédé d'intégration de double damasquinage pour un câblage à base de cuivre dans un empilement à faible constante diélectrique (120, 130, 140). Ce procédé met en oeuvre trois couches supérieures rigides de masquage (150, 160, 170) qui présentent des caractéristiques de sélectivité de gravure alternantes, par exemple, inorganique/organique/inorganique.
Bibliography:Application Number: WO2003US09700