MOTION COMPENSATED DE-INTERLACING IN VIDEO SIGNAL PROCESSING

A processing circuit for motion compensated de-interlacing of video signals, the processing circuit comprising: a line memory (21), a de-interlacing circuit (22), a frame memory (24), and a cache memory (25), in which a pixel mixer (29) is interposed between the cache memory (25) and the de-interlac...

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Bibliographic Details
Main Authors OJO, OLUKAYODE, A, KETTENIS, JEROEN, M
Format Patent
LanguageEnglish
French
Published 20.06.2002
Edition7
Subjects
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PICTORIAL COMMUNICATION, e.g. TELEVISION
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Summary:A processing circuit for motion compensated de-interlacing of video signals, the processing circuit comprising: a line memory (21), a de-interlacing circuit (22), a frame memory (24), and a cache memory (25), in which a pixel mixer (29) is interposed between the cache memory (25) and the de-interlacing circuit (22). L'invention se rapporte à un circuit de traitement pour le désentrelacement à compensation de mouvement de signaux vidéo. Ce circuit comprend : une mémoire de lignes (21), un circuit de déentrelacement (22), une mémoire d'images (24), et une mémoire cache (25), un mélangeur de pixels (29) étant interposé entre la mémoire cache (25) et le circuit de désentrelacement (22).
Bibliography:Application Number: WO2001EP13825