SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT, MULTI-LAYER PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD

A semiconductor element, wherein copper transition layers (38) disposed on die pads (22) of an IC chip (20) are incorporated in a multi-layer printed circuit board (10), whereby the IC chip (20) can be connected electrically to the multi-layer printed circuit board (10) without using lead parts and...

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Bibliographic Details
Main Authors WANG, DONGDONG, SAKAMOTO, HAJIME
Format Patent
LanguageEnglish
French
Japanese
Published 04.04.2002
Edition7
Subjects
BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
CURRENT COLLECTORS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
LINE CONNECTORS
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
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Summary:A semiconductor element, wherein copper transition layers (38) disposed on die pads (22) of an IC chip (20) are incorporated in a multi-layer printed circuit board (10), whereby the IC chip (20) can be connected electrically to the multi-layer printed circuit board (10) without using lead parts and sealing resin, the resin is prevented from remaining on an aluminum pad (24) by providing the copper transition layers (38) on the aluminum pad (24), and the connectability between the die pads (22) and via holes (60) and the reliability thereof can be increased. L'invention concerne un élément semi-conducteur. Des couches de transition de cuivre (38) disposées sur des plages de connexion (22) d'une puce CI (20) sont intégrées dans une carte à circuit imprimé multicouche (10). La puce CI (20) peut être connectée électriquement à la carte à circuit imprimé multicouche (10) sans utilisation d'éléments de connexion ou de résine d'étanchéité. On évite ainsi le dépôt de résine résiduelle sur une plage d'aluminium (24), d'où une fiabilité améliorée et une augmentation de la connectabilité entre les plages de connexion (22) et les trous d'interconnexion (60).
Bibliography:Application Number: WO2001JP03589