POLISHING PAD FOR A SEMICONDUCTOR SUBSTRATE

• Main Authors: ANJUR, SRIRAM, P, DOWNING, WILLIAM, C
• Format: Patent
• Language: English; French
• Published: 20.01.2000
• Edition: 7
• Subjects: ADHESIVES; BASIC ELECTRIC ELEMENTS; CHEMISTRY; DRESSING OR CONDITIONING OF ABRADING SURFACES; DYES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS; GRINDING; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FORELSEWHERE; METALLURGY; MISCELLANEOUS APPLICATIONS OF MATERIALS; MISCELLANEOUS COMPOSITIONS; NATURAL RESINS; PAINTS; PERFORMING OPERATIONS; POLISHES; POLISHING; SEMICONDUCTOR DEVICES; TOOLS FOR GRINDING, BUFFING, OR SHARPENING; TRANSPORTING

A polishing pad for polishing a semiconductor wafer which includes an open-celled porous substrate having sintered particles of synthetic resin. The porous substrate is a uniform, continuous and tortuous interconnected network of capillary passage. The pad includes a bottom surface that is mechanically buffed to improve the adhesion of an adhesive to the pad bottom surface. L'invention concerne un tampon à polir pour le polissage d'une plaquette en semiconducteur, qui comprend un substrat poreux à structure en alvéoles ouvertes renfermant des particules frittées de résine synthétique. Le substrat poreux se présente sous la forme d'un réseau interconnecté uniforme, continu et tortueux de passages capillaires. Le tampon comporte une surface inférieure brossée mécaniquement, ce qui permet d'améliorer l'adhérence d'un adhésif à ladite surface inférieure.