Apparatus and circuit for processing carrier aggregation

• Main Authors: Kim, In-Hyoung, Do, Joo-Hyun
• Format: Patent
• Language: English
• Published: 16.01.2024
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.