Semiconductor memory device

Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable...

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Main Authors NAKAKUMA TETSUJI, HIRANO HIROSHIGE, MURAKUKI YASUO, IWANARI SHUNICHI, GOHOU YASUSHI, MIKI TAKASHI, SAKAGAMI MASAHIKO, YAMAOKA KUNISATO
Format Patent
LanguageEnglish
Published 26.10.2010
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
Bibliography:Application Number: US20080155392