Memory system performing fast access to a memory location by omitting the transfer of a redundant address

A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address reg...

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Bibliographic Details
Main Authors OKADA TETSUHIKO, NISHII OSAMU, TAKEDA HIROSHI, HIRATSUKA NORIHARU, HAYASHI NOBUYUKI
Format Patent
LanguageEnglish
Published 24.08.2010
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
Bibliography:Application Number: US20020290367