Scalable stochastic successive approximation register analog-to-digital converter

Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate fir...

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Bibliographic Details
Main Authors Gordon, Eshel, Lakdawala, Hasnain, Degani, Ofir, Maerkovich, Sophia
Format Patent
LanguageEnglish
Published 12.06.2018
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION
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Summary:Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.
Bibliography:Application Number: US201615282622