Integrated circuit stack including a patterned array of electrically conductive pillars

The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically...

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Bibliographic Details
Main Authors Vogt, Eric E, Tucker, James L, Dougal, Gregor D
Format Patent
LanguageEnglish
Published 12.06.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
Bibliography:Application Number: US201615352405