III-V MOSFET with self-aligned diffusion barrier

A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source including III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial la...

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Bibliographic Details
Main Authors Sun, Yanning, Chu, Jack Oon, Yau, Jeng-Bang, Chan, Kevin K, Cheng, Cheng-Wei
Format Patent
LanguageEnglish
Published 17.04.2018
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source including III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer including silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer including transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer including transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.
Bibliography:Application Number: US201514870794